System and Method for High-Performance, Low-Power Data Center Interconnect Fabric

ABSTRACT

A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.

CROSS REFERENCE TO RELATED APPLICATIONS

This continuation patent application claims priority to co-pending U.S.Non-Provisional Patent Application having Ser. No. 12/794,996 filed Jun.7, 2010 entitled “SYSTEM AND METHOD FOR HIGH-PERFORMANCE, LOW-POWER DATACENTER INTERCONNECT FABRIC”, which claims priority to United StatesProvisional Patent Application having Ser. No. 61/256,723 filed Oct. 30,2009 entitled “SYSTEM AND METHOD FOR ENHANCED COMMUNICATIONS IN AMULTI-PROCESSOR SYSTEM ON A CHIP (SOC)”, both of these applicationshaving a common applicant herewith and being incorporated herein intheir entirety by reference.

FIELD

The disclosure relates generally to a switching fabric for acomputer-based system.

BACKGROUND

With the continued growth of the internet, web-based companies andsystems and the proliferation of computers, there are numerous datacenters that house multiple server computers in a location that istemperature controlled and can be externally managed as is well known.

FIGS. 1A and 1B show a classic data center network aggregation as iscurrently well known. FIG. 1A shows a diagrammatical view of a typicalnetwork data center architecture 100 wherein top level switches 101 a-nare at the tops of racks 102 a-n filled with blade servers 107 a-ninterspersed with local routers 103 a-f. Additional storage routers andcore switches. 105 a-b and additional rack units 108 a-n containadditional servers 104 e-k and routers 106 a-g FIG. 1 b shows anexemplary physical view 110 of a system with peripheral servers 111 a-bnarranged around edge router systems 112 a-h, which are placed aroundcentrally located core switching systems 113. Typically such anaggregation 110 has 1-Gb Ethernet from the rack servers to their top ofrack switches, and often 10 Gb Ethernet ports to the edge and corerouters.

However, what is needed is a system and method for packet switchingfunctionality focused on network aggregation that reduces size and powerrequirements of typical systems while reducing cost all at the same timeand it is to this end that the disclosure is directed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B illustrate a typical data center system;

FIG. 2A illustrates a computing unit that may include a universaladdress system and method;

FIG. 2B illustrates a computing system that may include a universaladdress system and method;

FIG. 2C is an overview of a network aggregation system;

FIG. 3 illustrates an overview of an exemplary data center in a racksystem;

FIG. 4 illustrates a high-level topology of a network aggregatingsystem;

FIG. 5A illustrates a block diagram of an exemplary switch of thenetwork aggregation system;

FIG. 5B illustrates the MAC address encoding;

FIG. 6 illustrates a first embodiment of a broadcast mechanism of thenetwork aggregation system;

FIG. 7 illustrates an example of unicast routing of the networkaggregation system;

FIG. 8 illustrates an example of fault-resistant unicast routing of thenetwork aggregation system;

FIG. 9 illustrates a second embodiment of a broadcast mechanism of thenetwork aggregation system;

FIG. 10 illustrates an exemplary system for management of power suppliedto multiple processors;

FIG. 11 illustrates an exemplary data structure that may be maintainedby a power management system shown in FIG. 10;

FIG. 12 an example of a process for power management;

FIG. 13 illustrates an example of a larger power management system;

FIG. 14 illustrates an exemplary process for system level powermanagement;

FIG. 15 illustrates an architectural overview of a multiprocessor chip;and

FIG. 16 illustrates more details of the switching fabric shown in FIG.15.

DETAILED DESCRIPTION OF ONE OR MORE EMBODIMENTS

The disclosure is particularly applicable to a network aggregationsystem and method as illustrated and described below and it is in thiscontext that the disclosure will be described. It will be appreciated,however, that the system and method has greater utility since the systemand method can be implemented using other elements and architecturesthat are within the scope of the disclosure and the disclosure is notlimited to the illustrative embodiments described below.

The system and method also supports a routing using a tree-like or graphtopology that supports multiple links per node, where each link isdesignated as an Up, Down, or Lateral link, or both, within thetopology. In addition, each node in the system maybe be a combinationcomputational/switch node, or just a switch node, and input/outpout(I/O) can reside on any node as described below in more detail. Thesystem may also provide a system with a segmented Ethernet Media AccessControl (MAC) architecture which may have a method of re-purposing MACIP addresses for inside MACs and outside MACs, and leveraging what wouldnormally be the physical signaling for the MAC to feed into the switch.The system may also provide a method of non-spoofing communication, aswell as a method of fault-resilient broadcasting, which may have amethod of unicast misrouting for fault resilience. In the context ofnetwork security, a spoofing attack is a situation in which one personor program successfully masquerades as another by falsifying data andthereby gaining an illegitimate advantage.

The system may also provide a rigorous security between the managementprocessors, such that management processors can “trust” one another. Inthe example system shown in FIG. 5A (which is described below in moredetail), there is a management processor within each SoC (the M3microcontroller, block 906, FIG. 5A). The software running on themanagement processor is trusted because a) the vendor (in this caseSmooth-Stone) has developed and verified the code, b) non-vendor code isnot allowed to run on the processor. Maintaining a Trust relationshipbetween the management processors allow them to communicate commands(e.g. reboot another node) or request sensitive information from anothernode without worrying that a user could spoof the request and gainaccess to information or control of the system.

The system may also provide a network proxy that has an integratedmicrocontroller in an always-on power domain within a system on a chip(SOC) that can take over network proxying for the larger onboardprocessor, and which may apply to a subtree. The system also provide amulti-domaining technique that can dramatically expand the size of aroutable fat tree like structure with only trivial changes to therouting header and the routing table.

FIG. 2A illustrates a computing unit 210 that is part of a distributedcomputing system and may include a universal address system and method.In one embodiment, each computing unit may be implemented on a singleintegrated circuit as shown in FIG. 2A. Each computing unit 210 mayinclude one or more processing cores 212, such as ARM processing cores,and an associated cache memory 214, a DDR controller 216, a not ANDlogic (NAND) flash memory interface 218, I/O interfaces 220, a powermanagement portion 222, a direct memory access (DMA)/virtual memorymanagement (VMM) support unit 224 described in more detail below and oneor more hardware accelerators 226.

FIG. 2B illustrates a distributed computing system 230 that may includea universal address system and method. Each computing system 230 may bea node in a processing system in which a plurality of nodes areconnected to each other over a link, such as a network. In addition tothe computing unit 210, each computing system 230 may further comprisedouble data rate (DDR) low power RAM 232, such as 512 Mb of low powerDDR RAM in one embodiment, which is direct access memory to thecomputing system, NAND flash memory 234, such as 2-8 Gb of NAND flashmemory in one embodiment, that acts as persistent storage and stores afile system, an interconnect 236 that connects this computing system tothe other computing systems over a link, such as a computer network, andsoftware 238, such as a Linux operating system, virtual memorymanagement (VMM) software and one or more optimized software functions.In one embodiment, the universal address system is implemented using theDMA and VMM support 224 of each computing unit 224 (See FIG. 2A) incombination with the VMM software 238 (shown in FIG. 2B). The DMA of thecomputing unit is a standard mechanism (common in many systems), whichcan be given a data movement task to perform by the system. In thisscenario, such a standard module would be told to copy a page of datavia the IO links to the local memory and then to report. The VMM supportis a similarly standard function consisting of both software andhardware that is used to check every memory access and convert thevirtual page to a physical page reference. In this scenario, theexisting mechanisms would use as the first level of the extendedmechanism and the VMM software would be used to further translate fromlocal physical page to universal address.

FIG. 2C illustrates a network aggregation system 300. The networkaggregation supports one or more high speed links 301 (thick lines),such as a 10-Gb/sec Ethernet communication, that connect an aggregationrouter 302 and one or more racks 303, such as three racks 303 a-c asshown in FIG. 3. In a first rack 303 a, the network aggregation systemprovides multiple high-speed 10 Gb paths, represented by thick lines,between one or more Smooth-Stone computing unit 306 a-d, such as servercomputers, on shelves within a rack. Further details of eachSmooth-Stone computing unit are described in more detail in U.S.Provisional Patent Application Ser. No. 61/256,723 filed on Oct. 30,2009 and entitled “System and Method for Enhanced Communications in aMulti-Processor System of a Chip (SOC)” which is incorporated herein inits entirety by reference. An embedded switch 306 a-d in theSmooth-Stone computing units can replace a top-of-rack switch, thussaving a dramatic amount of power and cost, while still providing a 10Gb Ethernet port to the aggregation router 302. The network aggregationsystem switching fabric can integrate traditional Ethernet (1 Gb or 10Gb) into the XAUI fabric, and the Smooth-Stone computing units can actas a top of rack switch for third-party Ethernet connected servers.

A middle rack 303 b illustrates another configuration of a rack in thenetwork aggregation system in which one or more Smooth-Stone computingunits 306 e,f can integrate into existing data center racks that alreadycontain a top-of-rack switch 308 a. In this case, the IT group cancontinue to have their other computing units connected via 1 Gb Ethernetup to the existing top-of-rack switch and the internal Smooth-Stonecomputing units can be connected via 10 Gb XAUI fabric and they canintegrate up to the existing top-of-rack switch with either a 1 Gb or 10Gb Ethernet interconnects as shown in FIG. 2C. A third rack 303 cillustrates a current way that data center racks are traditionallydeployed. The thin lines in the third rack 303 c represent 1 GbEthernet. Thus, the current deployments of data center racks istraditionally 1 Gb Ethernet up to the top-of-rack switch 308 b, and then10 Gb (thick line 301) out from the top of rack switch to theaggregation router. Note that all servers are present in an unknownquantity, while they are pictured here in finite quantities for purposesof clarity and simplicity. Also, using the enhanced SS servers, noadditional routers are needed, as they operate their own XAUI switchingfabric, discussed below.

FIG. 3 shows an overview of an exemplary “data center in a rack” 400according to one embodiment of the system. The “data center in a rack”400 may have 10-Gb Ethernet PHY 401 a-n and 1-Gb private Ethernet PHY402, Large computers (power servers) 403 a-n support search; datamining; indexing; Apache Hadoop, a Java software framework; MapReduce, asoftware framework introduced by Google to support distributed computingon large data sets on clusters of computers; cloud applications; etc.Computers (servers) 404 a-n with local flash and/or solid-state disk(SSD) support search, MySQL, CDN, software-as-a-service (SaaS), cloudapplications, etc. A single, large, slow-speed fan 405 augments theconvection cooling of the vertically mounted servers above it. Datacenter 400 has an array 406 of hard disks, e.g., in a Just a Bunch ofDisks (MOD) configuration, and, optionally, Smooth-Stone computing unitsin a disk form factor (for example, the green boxes in arrays 406 and407), optionally acting as disk controllers. Hard disk servers or SSdisk servers may be used for web servers, user applications, and cloudapplications, etc. Also shown are an array 407 of storage servers andhistoric servers 408 a,b (any size, any vendor) with standard Ethernetinterfaces for legacy applications.

The data center in a rack 400 uses a proprietary system interconnectapproach that dramatically reduces power and wires and enablesheterogeneous systems, integrating existing Ethernet-based servers andenabling legacy applications. In one aspect, a complete server orstorage server is put in a disk or SSD form factor, with 8-16 SATAinterfaces with 4 ServerNodes™ and 8 PCIe x4 interfaces with 4ServerNodes™. It supports disk and/or SSD+ServerNode™, using aproprietary board paired with a disk(s) and supporting Web server, userapplications, cloud applications, disk caching, etc.

The Smooth-Stone XAUI system interconnect reduces power, wires and thesize of the rack. There is no need for high powered, expensive Ethernetswitches and high-power Ethernet Phys on the individual servers. Itdramatically reduces cables (cable complexity, costs, significant sourceof failures). It also enables a heterogeneous server mixture inside therack, supporting any equipment that uses Ethernet or SATA or PCIe. Itcan be integrated into the system interconnect.

The herein presented aspects of a server-on-a-chip (SOC) with packetswitch functionality are focused on network aggregation. The SOC is nota fully functionally equivalent to an industry-standard network switch,such as, for example, a Cisco switch or router. But for certainapplications discussed throughout this document, it offers a betterprice/performance ratio as well as a power/performance ratio. Itcontains a layer 2 packet switch, with routing based onsource/destination MAC addresses. It further supports virtual local areanetwork (VLAN), with configurable VLAN filtering on domain incomingpackets to minimize unnecessary traffic in a domain. The embedded MACswithin the SOC do have complete VLAN support providing VLAN capabilityto the overall SOC without the embedded switch explicitly having VLANsupport. It can also wake up the system by management processornotifying the management processor on link state transitions toreprogram routing configurations to route around faults. Suchfunctionality does not require layer 3 (or above) processing (i.e., itis not a router). It also does not offer complete VLAN support, supportfor QoS/CoS, address learning, filtering, spanning tree protocol (STP),etc.

FIG. 4 shows a high-level topology 800 of the network system thatillustrates XAUI connected SoC nodes connected by the switching fabric.The 10 Gb Ethernet ports Eth0 801 a and Eth1 801 b come from the top ofthe tree. Ovals 802 a-n are Smooth-Stone nodes that comprise bothcomputational processors as well as the embedded switch. The nodes havefive XAUI links connected to the internal switch. The switching layersuse all five XAUI links for switching. Level 0 leaf nodes 802 d, e(i.e., N0n nodes, or Nxy, where x=level and y=item number) only use oneXAUI link to attach to the interconnect, leaving four high-speed portsthat can be used as XAUI, 10 Gb Ethernet, PCIe, SATA, etc., forattachment to I/O. The vast majority of trees and fat trees have activenodes only as leaf nodes, and the other nodes are pure switching nodes.This approach makes routing much more straightforward. Topology 800 hasthe flexibility to permit every node to be a combination computationaland switch node, or just a switch node. Most tree-type implementationshave I/O on the leaf nodes, but topology 800 let the I/O be on any node.In general, placing the Ethernet at the top of the tree minimizes theaverage number of hops to the Ethernet.

In more detail, the ovals shown in the tree-oriented topology in FIG. 6represent independent nodes within a computing cluster. FIG. 5Aillustrates one example implementation of an individual node of thecluster. When looking at a conventional implementation of a topologye.g. in FIG. 6, usually computing nodes are found in the lower levelleaf nodes (e.g. N00-N08), and the upper level nodes don't havecomputing elements but are just network switching elements (N10-N21).With the node architecture shown in FIG. 6A, the A9 Cores (905) may beoptionally enabled, or could be just left powered-off. So the upperlevel switching nodes (N10-N21) in FIG. 6 can be used as pure switchingelements (like traditional implementations), or we can power on the A9Cores module and use them as complete nodes within the computingcluster.

The switch architecture calls for a routing frame to be prepended to theEthernet frame. The switch operates only against fields within therouting frame, and does not inspect the Ethernet frame directly. FIG. 5a shows a block diagram of an exemplary switch 900 according to oneaspect of the system and method disclosed herein. It has four areas ofinterest 910 a-d. Area 910 a corresponds to Ethernet packets between theCPUs and the inside MACs. Area 910 b corresponds to Ethernet frames atthe Ethernet physical interface at the inside MACs, that contains thepreamble, start of frame, and inter-frame gap fields. Area 910 ccorresponds to Ethernet frames at the Ethernet physical interface at theoutside MAC, that contains the preamble, start of frame, and inter-framegap fields. Area 910 d corresponds to Ethernet packets between theprocessor of routing header 901 and outside MAC 904. This segmented MACarchitecture is asymmetric. The inside MACs have the Ethernet physicalsignaling interface into the routing header processor, and the outsideMAC has an Ethernet packet interface into the routing header processor.Thus the MAC IP is re-purposed for inside MACs and outside MACs, andwhat would normally be the physical signaling for the MAC to feed intothe switch is leveraged. MAC configuration is such that the operatingsystem device drivers of A9 cores 905 manage and control inside Eth0 MAC902 and inside ETH1 MAC 903. The device driver of management processor906 manages and controls Inside Eth2 MAC 907. Outside Eth MAC 904 is notcontrolled by a device driver. MAC 904 is configured in Promiscuous modeto pass all frames without any filtering for network monitoring.Initialization of this MAC is coordinated between the hardwareinstantiation of the MAC and any other necessary management processorinitialization. Outside Eth MAC 904 registers are visible to both A9 905and management processor 906 address maps. Interrupts for Outside EthMAC 904 are routable to either the A9 or management processor. The XGMACsupports several interruptible events that the CPUs may want to monitor,including any change in XGMII link fault status, hot-plugging or removalof PHY, alive status or link status change, and any RMON counterreaching a value equal to the threshold register.

In some cases, there may be Preamble, Start of Frame, and Inter-Framegap fields across XAUI, depending on the specific micro-architecture.The routing frame header processor may standardize these fields. TheXAUI interface may need some or all of these fields. In this case, therouting header processor at area 910 d needs to add these going into theswitch, and to remove them leaving the switch. To reduce the number ofbytes that need to be sent over XAUI, these three fields may be removed(if the XAUI interface allows it). In this case, the routing headerprocessor at area 910 b will need to strip these going into the switch,and add them back leaving the switch.

The routing frame header processor receives an Ethernet frame from aMAC, sending a routing frame to the switch. it also standardizes thepreamble, start of frame, and inter-frame gap fields, prepends a routingheader, and receives a routing frame from the switch, sending theEthernet frame into a MAC. This processor then strips the routing headerand standardizes the preamble, start of frame, and inter-frame gapfields. Note that all frames that are flowing within the fabric arerouting frames, not Ethernet frames. The Ethernet frame/routing frameconversion is done only as the packet is entering or leaving the fabricvia a MAC. Note also that the routing logic within the switch may changefields within the routing frame. The Ethernet frame is never modified(except the adding/removing of the preamble, start of frame, andinter-frame gap fields).

The routing frame is composed of the routing frame header plus the corepart of the Ethernet frame, and is structured as shown in Table 1,below:

TABLE 1 Routing Frame Header Ethernet Frame Packet RF MAC MAC Ethertype/Payload CRC32 Header destination Source Length (data and padding)

Note that the implementation assumptions for bit sizing are 4096nodes→12 bit node IDs. These fields may be resized during implementationas needed.

The routing frame header consists of the fields shown in Table 2, below:

TABLE 2 Width Field (Bits) Notes Domain ID 5 Domain ID associated withthis packet. 0 indicates that no domain has been specified. Mgmt Domain1 Specifies that the packet is allowed on the private management domain.Source Node 12 Source node ID Source Port 2 0 = MAC0, 1 = MAC1, 2 =MAC_management processor, 3 = MAC_OUT Dest Node 12 Destination node IDDest Port 2 0 = MAC0, 1 = MAC1, 2 = MAC_management processor, 3 =MAC_OUT RF Type 2 Routing Frame Type (0 = Unicast, 1 = Multicast, 2 =Neighbor Multicast, 3 = Link Directed) TTL 6 Time to Live—# of hops thatthis frame has existed. Switch will drop packet if the TTL threshold isexceeded (and notify management processor of exception). Broadcast ID 5Broadcast ID for this source node for this broadcast packet. ChecksumChecksum of the frame header fields. Total 46 +checksum

If a switch receives a packet that fails the checksum, the packet isdropped, a statistic counter is incremented, and the managementprocessor is notified.

The routing frame processor differentiates between several destinationMAC address encodings. As a reminder, MAC addresses are formatted asshown in FIG. 5 b. The following table describes the usage of the 3 byteOUI and 3 byte MC specific field within the MAC address. One of thenovel aspects of the system and method disclosed herein is the use ofadditional address bits to encode an internal to external MAC mapping,as shown also in the Table 3, below, in the second entry under “FabricInternal Node local address Hits MAC Lookup CAM”.

TABLE 3 MAC Address Type 3 bytes OUI 3 bytes NIC Specific OperationExternal Multicast bit Arbitrary Packet unicast Misses MAC not setrouted to Lookup CAM gateway node #. Fabric Internal Arbitrary Nodelocal address (meaning Packet unicast Node local low 2 bits—port unitrouted to address ID) are not present. MAC fabric node # Hits MAC LookupCAM for entry obtained from Lookup CAM marked as Node Local. MAC LookupCAM Fabric Internal Arbitrary Arbitrary Packet unicast Arbitrary MACrouted to address fabric node # Hits MAC obtained from Lookup CAM MACLookup CAM Node Encoded Unicast 10 bits: Packet Unicast LocallySS_MAC_NODE_ENCODED_MAGIC unicast administered 12 bits: Node ID routedto OUI == Switch 2 bits: Port ID Node ID. OUI Link Encoded Unicast 12bits: Packet sent Unicast Locally SS_MAC_LINK_ENCODED_MAGIC downspecific administered 7 bits: Reserved Link #. OUI == Switch 3 bits:Link # (0-4) OUI 2 bits: Port Multicast/ Multicast bit Arbitrary PacketBroadcast set broadcast routed through fabric and gateways. NeighborMulticast bit 12 bits: Packet sent Multicast set SS_NEIGHBOR_MCAST_MAGICthrough all Locally 12 bits: Reserved XAUI links to administeredneighboring OUI = Switch nodes and not OUI rebroadcast to other nodes

Further, other novel aspects can be found in Table 3 under “Node EncodedUnicast” as well as “Link Encoded Unicast,” allowing one internal nodeor link to address all external MAC sections, and the “NeighborMulticast” entry, allowing a multicast to neighboring nodes.

Note that the values SS_MAC_NODE_ENCODED_MAGIC andSS_MAC_LINK_ENCODED_MAGIC are constant identifiers used for uniquelyidentifying these MAC address types. The term “magic number” is astandard industry term for a constant numerical or text value used toidentify a file format or protocol. These magic numbers are configuredin two registers (magicNodeEncodedMAC and magicLinkEncodedMAC thatdefault to standard values during hardware initialization, but allow themanagement processor software to change them if necessary.

The header processor contains a MAC Lookup CAM (Content AddressableMemory), macAddrLookup, that maps from 6 byte MAC addresses to 12-bitNode IDs, as shown in Table 4, below.

TABLE 4 MAC Lookup CAM Input MAC Lookup CAM Output Node Local MACAddress Node ID Port ID 1 bit 6 bytes 12 bits 2 bits

The number of rows in this CAM is implementation dependent, but would beexpected to be on the order of 256-1024 rows. The management processorinitializes the CAM with Node ID mappings for all the nodes within theSS fabric. There are two types of rows, depending upon the setting ofthe Node Local bit for the row. The Node Local field allows a 4:1compression of MAC addresses in the CAM for default MAC addresses,mapping all four MACs into a single row in the CAM table, which is Table5, below.

TABLE 5 MAC Address Node Type Local MAC Address Port ID Node 1 A NodeEncoded Address refers to a Smooth Stone Taken from Local assigned MACaddress for a node. It encodes the port # low 2 bits of (MAC0, MAC1,management processor, Rsvd) into a 2- MAC Address bit Port ID in thelowest two bits of the NIC address Input field. Ignores low 2 bitsduring match. Arbitrary 0 Matches against all 6 bytes Taken from CAMOutput field

The arbitrary rows in the CAM allow mapping of the MAC address aliasesto the nodes. Linux (and the MACs) allow the MAC addresses to bereassigned on a network interface (e.g., with ifconfig eth0 hw ether00:80:48:BA:d1:30). This is sometime used by virtualization/cloudcomputing to avoid needing to re-ARP after starting a session.

The switch architecture provides for a secondary MAC Lookup CAM thatonly stores the 3 bytes of the NIC Specific part of the MAC address forthose addresses that match the Switch OUI. The availability of thislocal OUT CAM is determined by the implementation. See Table 6, below.

TABLE 6 MAC Lookup CAM Input MAC Lookup CAM Output MAC Address NICSpecific Node ID Port ID 3 bytes 12 bits 2 bits

The maximum number of nodes limitation for three types of MAC addressencodings may be evaluated as follows:

1. Default MAC Addressees—management processor sets Node Local mappingsfor each of the nodes in the fabric. There is one entry in the CAM foreach node. Max # of nodes is controlled by maximum # of rows in the MACAddress Lookup CAM,

2. Node Encoded Addresses—All the MACs are reprogrammed to use NodeEncoded Addresses. In this way the Node IDs are directly encoded intothe MAC addresses. No entries in the MAC Lookup CAM are used. Max # ofnodes is controlled by maximum # of rows in the Unicast lookup table(easier to make big compared to the Lookup CAM). Note that this alsogives us some risk mitigation in case the MAC Lookup CAM logic isbusted. Provides use case for the node encoded addresses idea.

3. Arbitrary MAC Address Aliases—Takes a row in the CAM. As an example,a 512-row CAM could hold 256 nodes (Node local addresses)+1 MAC addressalias per node.

Since the Lookup CAM is only accessed during Routing Header creation,the management processor actually only needs to populate a row if theMAC address within the fabric is being used as a source or destinationMAC address within a packet. In other words, if two nodes never willtalk to each other, a mapping row does not need to be created. Butusually the management processor won't have that knowledge, so it'sexpected that mappings for all nodes are created in all nodes. Also notethat even if an entry is not created in the Lookup CAM, the routing willactually still succeed by routing the packet out the Ethernet gateway,through an external router, back into the Fabric, to the destinationnode.

Table 7 defines how to set fields within the Routing Header for all thefields except for destination node and port.

TABLE 7 Field Set To Domain ID Set to the macDomainID field for the MACthat the packet came from. Mgmt Set to the macMgmtDomain field for theMAC that Domain the packet came from. Source Node Switch Node ID SourcePort Source MAC Port ID RF Type Multicast (if dstMAC multicast and notNeighbor Multicast format) Neighbor Multicast (if dstMAC multicast andis Neighbor Multicast format) Link Directed (is Link Encoded format)Unicast (if not one of the above) TTL 0 Broadcast If dstMAC is unicast -Set to 0 ID If dstMAC is multicast - Set to incremented local broadcastID (bcastIDNext++ & 0xf)

Table 8 defines how to set destination node and port for addresseswithin the fabric:

TABLE 8 Field: Field: Destination Destination Case Node Port NodeEncoded Dest Address Dest Node Dest Port Link Encoded Dest AddressEncoded Link Dest Port Hits Lookup CAM (node local) CAM Dest Node DestMAC (low 2 bits) Hits Lookup CAM (not node local) CAM Dest Node CAM DestPort

Table 9 defines how to set destination node and port for addressesoutside the fabric:

TABLE 9 Field: Field: Destination Destination Case Node Port Came in anOUT Ethernet, but no Drop packet, update statistics counter secondarygateway defined Came in an OUT Ethernet, andsecondaryEthGatewayNode[OUT] OUT secondary gateway defined From anInside MAC, but no Drop packet, update statistics primary gatewaydefined counter, and notify management processor From an Inside MAC, andprimaryEthGatewayNode[fromPort] OUT primary gateway defined

Additionally, the management processor software architecture of thesystem and method disclosed here currently depends on the ability ofmanagement processor nodes to “trust” each other. This more rigoroussecurity on management processor to management processor communicationis desirable, as well a better security on private management LANsacross the fabric. This fabric issue may be mitigated by simplydefining, for environments that require multiple “hard” securitydomains, that customers simply don't mix security domains within afabric. In such cases, it may be possible to connect 14-node boards tothe top of rack switch, allowing customers to have VLAN granularitycontrol of each 14-node board.

The multi-domain fabric architecture that has been described addressesthe lack of VLAN support by creating secure “tunnels” and domains acrossthe fabric, and it can interoperate with VLAN protected router ports ona 1:1 basis.

The approach to domain management in the system and method disclosedhere is as follows: Support multiple domain IDs within the fabric. Alloweach of the MACs within a node (management processor, MAC0, MAC1,Gateway) to be assigned to a domain ID individually (and tagged withdomain 0 if not set). Allow each of the MACs within a node to have a bitindicating access to the management domain. The domain IDs associatedwith a MAC could only be assigned by the management processor, and couldnot be altered by the A9. For frames generated by MACs (both inside andoutside), the routing frame processor would tag the routing frame withthe domain ID and management domain state associated with that MAC.Domains would provide the effect of tunnels or VLANs, in that they keeppackets (both unicast and multicast) within that domain, allowing MACsoutside that domain to be able to neither sniff or spoof those packets.Additionally, this approach would employ a five-bit domain ID. It wouldadd options to control domain processing, such as, for example, a switchwith a boolean per MAC that defines whether packets are delivered withnon-defined (i.e., zero) domain ID, or a switch that has a boolean perMAC that defines whether packets are delivered with defined (non-zero)but non-matching domain IDs. A further option in the switch could turnoff node encoded MAC addresses per MAC (eliminating another style ofpotential attack vector).

To keep management processor to management processor communicationsecure, the management domain bit on all management processor MACs couldbe marked. Generally, the management processor should route on domain 1(by convention). Such a technique allows all the management processor'sto tunnel packets on the management domain so that they cannot beinspected or spoofed by any other devices (inside or outside thefabric), on other VLANs or domains. Further, to provide a securemanagement LAN, a gateway MAC that has the management domain bit setcould be assigned, keeping management packets private to the managementprocessor domain. Additionally, the switch fabric could support“multi-tenant” within itself, by associating each gateway MAC with aseparate domain. For example, each gateway MAC could connect to anindividual port on an outside router, allowing that port to beoptionally associated with a VLAN. As the packets come into the gateway,they are tagged with the domain ID, keeping that traffic private to theMACs associated with that domain across the fabric.

The switch supports a number of registers (aka CSRs, aka MMRs) to allowsoftware or firmware to control the switch. The actual layout of theseregisters will be defined by the implementation. The fields listed inTable 10 are software read/write. All these registers need to have amechanism to secure them from writing from the A9 (could be secure modeor on a management processor private bus).

TABLE 10 Field Size Notes Adaptive 1 bit Adaptive unicast routingenabled. broadcastLateral 1 bit Enable to have broadcasts go throughlateral links, rather than just Up and Down links. Turning this off willwork for most topologies and will reduce # duplicate broadcast packets.intPortBroadcastVec 4 bits Vector of ports to send internally generatedbroadcast packet into. extPortBroadcastVec 4 bits Vector of ports tosend externally generated broadcast packet into. linkDir[LINKS] Array[LINKS] x Specifies link direction for each link 2 bits (0 = DOWN, 1 =LATERAL, 2 = UP, 3 = Rsvd) linkState 5 bits Link state vector for eachof the 5 links. Bit set indicates that link is active (trained andlinked). linkType[LINKS] Array [LINKS] x Specifies type of each link 2bits (0 = No Link, 1 = XAUI, 2 = Ethernet} localBroadcastM3Snoop 1 bitWhen set, then we'll always send a copy of the locally initiatedbroadcast into the management processor. The use case here is where themanagement processor wants to see the gratuitous ARPs that are locallyinitiated so that it can communicate across the management processorfabric and add corresponding entries into the local unicast routingtables. macAddrLookup Lookup CAM which is MAC address lookup CAM toconvert MAC described elsewhere in addresses to Node IDs. the documentmacAcceptOtherDomain[MAC] 1 bit[MAC] Defines that the MAC acceptspackets that are tagged with a non-zero, non-matching domain ID.macAcceptZeroDomain[MAC] 1 bit[MAC] Defines that the MAC accepts packetsthat are not tagged with a domain (i.e. 0 domain) macDomainID[MAC] 5bits[MAC] Defines the Domain ID for each of the 4 MACs. A value of 0indicates that the domain ID for that MAC is not set. macMgmtDomain[MAC]1 bit[MAC] Defines that the MAC may access the management domain.Setting this tags the management domain in the routing frame, as well asallows the switch to route management frame packets into this MAC.magicNodeEncodedMAC 10 bits Magic number for Node Encoded MAC addressesmagicLinkEncodedMAC 12 bits Magic number for Link Encoded MAC addressesmaxTTL 6 bits Maximum TTL count allowed in a routing header. Exceedingthis number of hops causes the switch to drop the packet, update astatistic counter, and inform the management processor. myNodeID 12 bitsNeed not be contiguous. Subtree's should ideally be numbered within arange to facilitate subtree network proxying. myOUI 3 bytes 3 upperbytes of MAC addresses in fabric. Should be the same for all nodes inthe fabric. nodeRangeEnable 1 bit Enables the expanded Node ID matchingof [nodeRangeLo, nodeRangeHi]. Used for Network Proxying through asubtree. When enabled, a packet will be routed into the node (ratherthan through the node) if either DstNode == myNodeID OR (nodeRangeLo <=DstNode <= nodeRangeHi). nodeRangeHi 12 bits Enabled withnodeRangeEnable. Specifies high node ID of node range match. nodeRangeLo12 bits Enabled with nodeRangeEnable. Specifies low node ID of noderange match. noFlowControl 1 bit When enabled, there will be no flowcontrol. portRemap[INT_PORTS]; Array [INT_PORTS] x Allows remapping ofincoming destination 2 bits port IDs to the internal port where it'll bedelivered. This register defaults to an equivalence remapping. Anexample of where this will get remapped is during Network Proxy wherethe management processor will remap MAC0 packets to be sent to themanagement processor. INT_PORTS = 4. Array elements are the Portsenumeration (management processor, MAC0, MAC1, OUT). 2 bits contents isthe Ports enumeration. primaryEthGatewayNode[INT_PORTS] Array[INT_PORTS] Specifies Node ID of primary Ethernet of 12-bit gateway forthis node. Packets destined to node IDs that aren't within the fabricwill get routed here. promiscuousPortVec 4 bits Can be configured forPromiscuous Mode allowing traffic on one or more links to be snooped bythe management processor or A9s in order to collect trace data or toimplement an Intruder Detection System (IDS). This causes all trafficpassing through the switch to be copied to the internal ports defined bythis port vector. routeForeignMACsOut 1 bit When enabled, a MAC addressthat does not contain a myOUI address, will not check the MAC lookupCAM, and will get treated as a MAC lookup CAM miss, thus getting routedto the gateway port. This saves latency in the common case of notpopulating the CAM with foreign MAC aliases.secondaryEthGatewayNode[INT_PORTS] Array [INT_PORTS] Specifies Node IDof secondary Ethernet of 12-bit gateway. Incoming (from OUT) packetsrouting through the fabric will be sent here. unicastPortsFromOtherExt 1bit An incoming unicast from an external Gateways gateway will get thegateway node put into the source node field of the routing header. Uponreaching the destination node, this bit will be checked. When the bit isclear, the external gateway node must match the destination gateway nodefor it to be delivered to internal ports. This is to handle the casewhere the fabric is connected to an external learning switch that hasn'tyet learned the mac/port relationship, and floods the unicast packetdown multiple ports. This will prevent a fabric node from getting theunicast packet multiple times. unicastRoute[NODES] Array [NODES] of Linkvector of unicast next route. 10 bits is 2- 10 bits bit weight for eachof 5 links.

The registers shown in Table 11 are contained within the Switchimplementation, but need not be software accessible.

TABLE 11 Field Size Notes bcastIDNext 5 bits Next broadcast sequence IDto issue next. Hardware will increment this for each broadcast packetinitiated by this node. bcastIDSeen[BCAST_ID_LEN] Array [BCAST_ID_LEN]FIFO list of broadcast tags seen by of 5 bits. this node.bcastIDSeenNext # bits to index into Next array position intoBCAST_ID_LEN bcastIDSeen[ ] to insert a broadcast tag.

Note that software should be able to update the routing tables(unicastRoute) and the macAddrLookup CAM atomically with respect toactive packet routing. One implementation will be to hold off routingaccess to these tables during an update operation.

Broadcast/Multicast Routing

FIG. 6 shows an exemplary broadcast mechanism 1000 according to oneaspect of the system and method disclosed herein. The link between nodesN10 1001 and N21 1002 is down, as indicated by the dashed line 1003.During routing header generation of multicast packets, the source nodeputs an incremented broadcast ID for that source node in the routingframe (rframe.bcastID). When a node receives a multicast routing frame(i.e. rframe.rfType==Multicast∥rframe.rfType==NeighborMulticast), itchecks to see whether it has already seen this broadcast packet. Thecheck is done by accessing the bcastIDSeen CAM with a tag formed withthe broadcast source node and the broadcast ID. If it has already beenseen (i.e. CAM hit), no action is be performed. If the broadcast framehas not been seen before, it broadcasts it to appropriate internal portsand external gateways (intPortBroadcastVec register) and rebroadcasts itthrough all outward XAUI links except for the link it came in on. Notethat it only broadcasts through laterals if the broadcastLateralregister is set. It is unnecessary to broadcast laterals on mosttopologies, and doing so may reduce the number of duplicated broadcastpackets by disabling it. It then adds this broadcast tag to thebcastIDSeen CAM in FIFO order. In FIG. 7, N041004 initiates a broadcastto all neighbors, i.e., N111105. N11 has not seen the packet, so itbroadcasts to all non-incoming neighbors, which, in this example, areN21 1002, N201006, N03 1007, and N05 1008, and accepts the packetinternally. Nodes N03 and N05 haven't seen the packet, so they acceptthe broadcast internally and are done. N21 hasn't seen the packet, so itbroadcasts the packet to all active, non-incoming links (e.g., N10, N121009), and accepts the packet internally. N20 broadcasts the packet toall active, non-incoming links (i.e., N12), and accepts the packetinternally. N10 broadcasts down to N00 1010, N011011, and N02 1012. N12rebroadcasts to N06 1013, N07 1014, N08 1015 and to one of N21 and N20(the one it didn't get the broadcast packet from). Note that one of N20and N21, and N12, see the packet twice. They take action only on theirfirst instance, the secondary times it hits the broadcast CAM as aduplicate, and the packet is ignored.

Unicast Routing Unicast to Other Node

Unicast routing (as shown in FIG. 7) is responsible for routingnon-multicast (i.e. unicast) packets to the next node, This is done byutilizing a software computed unicastRoute[ ] next node routing tablethat provides a vector of available links to get to the destinationnode.

-   -   Condition    -   rframe.rfType==Unicast    -   Routing

There are substantial complexities related to routing around faults.Fault free routing and routing around faults will be discussedseparately.

Traditionally in tree routing, the packet will be routed upward until acommon parent of (source, destination) is reached. This upward routingcan be deterministic, oblivious, or adaptive. The packet is then routeddownward to the destination using deterministic routing.

As an example, FIG. 7 illustrates a packet routing from node N00 1010 toN08 1015. The packet is routed in the upward phase to the commonancestor (N21) through node N101001, and then a descent phase to thedestination.

Note that during the upward phase at node N10, there are two candidatelinks (N10,N21) and (N10,N20). The first candidate link could be chosendeterministically, or an adaptive algorithm could dynamically selecteither of the links. But, once the node reaches the common ancestor andturns downward, there are no redundant paths (in general) for the nodeto reach the destination.

Unicast Routing in the Presence of No Faults

Each link is annotated within this unicastRoute table with a 2-bitlinkWeight where software can express the relative cost/distance to thedestination node via this link. By convention, link weights shouldrepresent:

-   -   0=No route    -   3=Direct next-hop connection    -   1 and 2=Software computed relative costs. As an example if there        are routes across 3 links with costs of 2 hops, 3 hops, and 6        hops, the first two links could be assigned weight=2 and the 6        hops path could be assigned weight=1.

Algorithm for fault-free unicast routing:

-   -   Get link weight vector from the unicast routing table        -   linkWeightVector=unicastRoute[rframe.dstNode]    -   Remove link that it came in on to remove possibility of sending        it back    -   Remove any links that are not up    -   At this point, have a candidate list of links with associated        link weights.    -   Iterate through link weights, starting with highest priority (3)        down through 1. Gather candidate list of links at this priority,        stopping once the candidate list has at least one link. The        result is a candidate list of links at the highest priority. As        an example, if there are 2 links at weight=2, and 2 links at        weight=1, the prioritized candidate list will contain the two        links at weight-2.    -   The adaptive register is checked to determine whether to do        adaptive or deterministic routing.        -   adaptive==0 indicates that deterministic routing is to be            used, so the first link is chosen from the prioritized            candidate list.        -   adaptive==1 indicates that adaptive routing is to be used.            The switch implementation will choose an algorithm for            adaptively choosing the target link from the prioritized            candidate list. This adaptive algorithm could be as simple            as round-robin around the list. Alternatively, may choose to            factor in other attributes e.g. FIFO free depth, link speed,            . . .            -   An implementation option could be to add a register                option to allow the router to adaptively choose from all                non-zero weights, or to only adaptively choose from the                highest priority candidate lists.    -   The packet is sent out the selected link.

Fault-Resilient Unicast Routing

A couple of issues contribute to the complexity of fault-resilientunicast routing:

-   -   The desire to do fault routing with only localized knowledge. A        node implicitly knows that a link is down to a neighbor node. We        choose a design to avoid having to communicate that a link (or        node) goes down elsewhere in the fabric due to the complexities        of maintaining a global, unified state in the presence of        failures.    -   The nature of routing in a tree. During the ascent phase of        packet routing, links can be adaptively chosen from redundant        links so it can be straightforward to avoid a link with the        normal adaptive link selection.    -   But, once the packet starts descending, traditionally there is        not redundant paths for the descent path (that follow the        routing rules), so fault routing can become challenging.    -   FIG. 8 illustrates a link failure (N10,N21) and unicast routing        selected the (N10, N20) link using the normal adaptive routing        algorithm previously described. But note, if the packet is        routed up to N20 and link (N20,N12) is down, it has no easy path        to get to the destination.

We have two approaches to handling routing around fails:

-   -   Software can compose alternative but non-desirable routes with        weight=1. We'll call these escape routes. These are low priority        routes that may violate the strict routing rules used during        routing around faults. As an example, if the link (N20, N12) was        down, the unicastRoute[N08] entry for N20 could contain link to        N12 with weight-2 and a link to N11 with weight=1. In this way,        the normal adaptive routing algorithms will automatically do the        N20->N11->N21->N12->N08 path.    -   The fabric architecture includes a technique that we refer to as        “misrouting”. Misrouting provides for iterative backtracking.    -   Both of these techniques will provide substantial unicast        fault-resilience.

Unicast Misrouting

As an example, consider the following topology, with 3 links 1101, 1102and 1103 that have failed (shown in FIG. 9). Consider a unicast routefrom N0 to N3. We'll consider the following routing to understand themisrouting technique, understanding that this is only one of severalroutes that could have been chosen adaptively.

-   -   Packet routed N0 to N6.    -   Packet routed N6 to N10    -   N10 sees that it has no paths to get to N3, other than the link        it came in on. N10 sets the misrouting bit in the routing        header, and sends it back to N6.    -   N6 sees that the packet is being misrouted, sets the bit for the        N 10 link in the misrouteVector in the routing header, chooses        an alternative link that has not been misrouted, and sends the        packet to N11.    -   N11 sees that it has no path to N3, other than the link it came        in on. misrouting bit is already on, and sends it back to N6.    -   N6 sees that the packet is being misrouted, adds N11 link to the        misrouteVector (now contains N10 and N11 link IDs), chooses an        alternative link that has not been misrouted, and sends it N7.    -   N7 sees that the misrouting bit is set, but does have a valid        link to N3 (to N12), and thus clears the misrouting bit in the        header, and forwards the packet to N 12.    -   N12 sends to N9.    -   N9 unicastRoute now likely contains link to N3 (weight=3) and        link to N8 (weight=2). Normal adaptive routing will not choose        the direct link to N3 since it's down, and will route the packet        to N8, then finally to N3.    -   If N6 had exhausted its list of candidate links (meaning the        misrouleVector masked them all), the implementation then has two        choices:        -   drop the packet and inform the M3 of the failure to route.        -   clear the misrouteVector leaving misrouting set, and forward            the packet through one of the downward facing links (if one            exists). This will retry misrouting at one layer lower. The            implementation may want to have a register bit            (enableRecursiveMisrouting) to enable this retry at lower            layer option.            There is a register enableMisrouting that allows software to            control whether the switch will initiate the misrouting            algorithm.

Multi-Domaining

Also known to the inventors is Multi-Domaining, whose goal is toincrease the addressability of nodes to a large number of nodes (e.g.,64 K nodes), without having to increase the size of the unicast routingtable to 64 K nodes.

As currently described, the unicast routing table is a single-dimensionarray indexed by node number (i.e. 0 to MAX_NODES-1), where a typicalimplementation will be between 256 and 4 K nodes.

This section will now describe how the current architecture is alteredto support multiple domains, with 64 K max nodes.

-   -   The node namespace is changed from a node ID from 0 to        MAX_NODES-1, to a 2-tuple of (domain ID, node ID), where both        domain ID and node ID range from 0 to 255. So, there can        effectively be 256 domains where each domain can contain up to        256 nodes.    -   The unicast routing table is changed from a single dimension        table of size MAX_NODES, to a two-dimension table of size 256.        The unicast routing table is now changed from a structure of        unicastRoute[NODES] to unicastRoute[2][256].

Local domain routing: When routing to a node within this domain, theunicast routing table is accessed as unicastRoute[0][node ID], andprovides a weighted link vector to route to the specified node ID fromthe current node.

-   -   -   Remote domain routing: When routing to a node within a            remote domain, the unicast routing table is accessed as            unicastRoute[1][domain ID], and provides a weighted link            vector to route to the specified domain ID from the current            node.

    -   Routing frame: One bit is added to the routing frame, dstRemote,        which is set true when routing to a remote domain.

    -   Locally administered MAC addresses: The section below describes        the Node Encoded

Unicast MAC address encoding as follows:

Node Unicast 10 bits: Encoded Locally SS_MAC_NODE_ENCODED_MAGIC Unicastadministered 12 bits: Node ID OUI == Switch 2 bits: Port ID OUI

This gets altered for multi-domaining as follows:

Node Unicast 6 bits: Encoded Locally SS_MAC_NODE_ENCODED_MAGIC Unicastadministered 8 bits: Domain ID OUI == Switch 8 bits: Node ID OUI 2 bits:Port ID

-   -   Creating the routing frame header: Table 2 describes the        algorithms for creating the routing frame header. This is        augmented in the multi-domaining case by:

if ( dstDomain == myDomainID ) { // Route to local domainrframe.dstRemote = false; rframe.dstNode = dstNode; } else { // Route toremote domain rframe.dstRemote = true; rframe.dstNode = dstDomain;

Network Proxy

The concept of network proxy is the ability of the main processors (FIG.5A, 905) to maintain network presence while in a low-powersleep/hibernation state, and intelligently wake when further processingis required. There are several architectural features related to NetworkProxy:

-   -   There is a CSR (portRemap) to allow the remapping of Port IDs.        In effect, when the switch is to deliver a packet to an internal        MAC0 port (e.g. FIG. 5A, 902), this Port Remapping CSR allows        software to remap MAC0 to the management processor MAC (e.g.        FIG. 5A, 907) and have the packet delivered to the management        processor for Network Proxy processing. This remapping CSR could        also be used to remap MAC1 traffic to MAC0, or MAC1 traffic to        the management processor.    -   Normally, the switch looks at the destination node ID of the        routing frame to decide whether the packet is delivered to an        internal port within the node, or gets routed to other XAUI        connected nodes. This is done by matching Destination Node ID to        “My Node ID”. The Node ID Match register (nodeRangeLo,        nodeRangeHi) causes the packet to be delivered to an internal        port within the node if        nodeRangeLo<=Destination_Node<=nodeRangeHi∥myNodeID==Destination_Node.        This allows a node to proxy for a subtree of nodes.        A typical use sequence would be of the form:    -   Management processor maintains the IP to MAC address mappings        for MAC0 and MAC1 on the node. This can be done via either        explicit communication of these mappings from the main processor        OS to the management processor, or can be done implicitly by        having the management processor snoop local gratuitous ARP        broadcasts.    -   The main processor coordinates with the management processor to        go to a low power dormant state. During this transition, the        management processor sets up the Port ID remapping CSR to route        MAC0 and MAC1 traffic to the management processor.    -   The management processor processes any incoming MAC0/MAC1        packets. There are 3 categories of processing:    -   Respond to some classes of transactions that require simple        responses (e.g. ARP responses and ICMP ping).    -   Dump and ignore some classes of packets, typically unicast or        broadcast packets that are targeting other computers.    -   Decide that the main processor must be woken to process some        classes of packets. The management processor will wake the main        processor, undo the Port ID remapping register, and re-send the        packets back through the switch where they will get rerouted        back to MAC0/1.

Wake-on-LAN Magic Packet

In a traditional desktop computer, the computer to be woken is shut down(sleeping, hibernating, or soft off; i.e., ACPI state G1 or G2), withpower reserved for the network card, but not disconnected from its powersource. The network card listens for a specific packet containing itsMAC address, called the magic packet, broadcast on the broadcast addressfor that particular subnet (or an entire LAN, though this requiresspecial hardware or configuration). The magic packet is sent on the datalink or layer 2 in the OSI model and broadcast to all NICs within thenetwork of the broadcast address; the IP-address (layer 3 in the OSImodel) is not used. When the listening computer receives this packet,the network card checks the packet for the correct information. If themagic packet is valid, the network card takes the computer out ofhibernation or standby, or starts it up.

The magic packet is a broadcast frame containing anywhere within itspayload: 6 bytes of ones (resulting in hexadecimal FF FF FF FF FF FF),followed by sixteen repetitions of the target computer's MAC address.Since the magic packet is only scanned for the string above, and notactually parsed by a full protocol stack, it may be sent as a broadcastpacket of any network- and transport-layer protocol. It is typicallysent as a UDP datagram to port 0, 7 or 9, or, in former times, as an IPXpacket.

Using the Network Proxy architecture just described, the managementprocessor can support these Wake-On-LAN packets. It will get thesebroadcast packets, will know the MAC addresses for the other MACs on thenode, and be able to wake up the main processor as appropriate. Nofurther functionality is needed in the switch to support theseWake-on-LAN packets.

Power Control Features

A system and method to manage the supply of power to large sets ofprocessors or processor cores in an efficient, closed-loop manner areprovided such that rather than the system supplying power that may ormay not be used, a processor would request power based on the computingtask at hand, which request would then be sent to the power supplysystem and thus power made available. Further needed is bidirectionalcommunication between the CPU(s) and the power supply stating it has acertain limit, and rather than giving each processor its desired amountof power, said system may give a processor an allocation based onprorated tasks.

Additionally needed is a method of prioritization that may be used toreallocate power among processors, so the allocation does not have to bea linear cut across the board.

Some of the leading processor architectures have a thermal managementmode that can force the processor to a lower power state; however noneat present time imposes similar power reduction dynamically based on theavailable power resources of the system, as they assume that sufficientpower is always available.

Each processor typically can run in a number of power states, includinglow power states where no processing occurs and states where a variableamount of execution can occur (for example, by varying the maximumfrequency of the core and often the voltage supplied to the device).This latter mechanism is commonly controlled by monitoring the loadingof the node, and if the load is low, decreasing the maximumfrequency/voltage of the CPU (the frequency and voltage of the corewould be adjusted downward so as to not exceed the power limit set inorder to keep the load below the capability limit of the power supply)until the amount of idle is reduced. The reverse is also often the case:if loading is high the frequency/voltage can be increased. Predictivemechanisms also exist where queued transactions are monitored, and ifthe queue is short or long the voltage and frequency can be alteredappropriately. Finally, in some cases a computational load (specificallyin the cloud nature of shared threads across multiple cores of multipleprocessors) is shared between several functionally identical processors.In this case it's possible to power down (or move into a lower powerstate) one or more of those servers if the loading is not heavy.

Currently there is no connection between power supply generation to theprocessors and the power states of each processor. Power supplies areprovisioned so that each processor can run at maximum performance (orclose to it) and the redundancy supplied is sufficient to maintain thislevel, even if one power supply has failed (in effect double the maximumexpected supply is provided). In part, this is done because there is noway of limiting or influencing the power state of each processor basedon the available supply.

A similar situation applies to cooling in an array of multipleprocessors, although due to the slow increase of temperature, it can bemonitored and capacity can be turned on or off (e.g., increase or slowfans). Based on the currently used capacity, enough capacity must stillbe installed to cool the entire system with each system at peakperformance (including any capacity that might be powered down throughfailure or maintenance).

In effect, the capacity allocated in both cases must be higher thanabsolutely necessary, based on the inability to modulate design whencapacity limits are approached. This limitation also makes it difficultto install short-term peak clipping capacity that can be used to relievesudden high load requirements (as there is no way of reducing the loadof the system when it is approaching the limits of that peak store). Asan example, batteries or any other means of storing an energy reservecould be included in the power supply system to provide extra powerduring peaks; however, when they approach exhaustion the load would needto be scaled down. In some cases, cooling temperatures could simply beallowed to rise for a short period.

FIG. 10 shows an overview of an exemplary system 2100 for management ofpower supplied to multiple processors according to one embodiment of thecurrent disclosure. An array of 16 processors 2101 a-p is shown. Eachprocessor has its own complete computing system, with memory andcommunication interconnection buses, a power feed, etc. All of theseelements of each processor's system are well known in current art andare not shown here, for reasons of simplicity and clarity. Processor2101 a has an operating system with multiple programs 2101 a 1-n. One ofthese programs, 2101 ax, is of particular interest. It is the piece thatcommunicates with the system management software of the currentdisclosure, described in greater detail in the discussion of FIG. 12,below. The system management software can actually run on any one of theprocessors 2101 a-p, or it can run on a separate, dedicated processor(not shown). A power supply unit (PSU) 2102 gets a main feed 2103 anddistributes it through subfeeds 2103 a-p to each of the processors 101a-p according to their individual needs. In some cases more than oneprocessor 2101 b-p can have similar software 2101 b 1-n through 2101 p1-n, including 2101 bx-px.

FIG. 11 shows an exemplary table 2200 that could be maintained by apower management system such as management system 2100, for example, asdescribed in FIG. 10. Each row 2201 a-p contains records of parameters2202 a-e that are recorded in columns. They may be updated from time totime as necessary, either if certain changes occur or on an intervalbasis, etc. It is clear that the five parameters 2202 a-e are onlyexemplary of any of a great variety of parameters that may be includedin table 2200, so the number of parameters is not restricted to fiveonly. In this example, parameters are (reading left to right) CPU ID,actual current usage, desired usage based on tasks awaiting execution bythe CPU, permitted usage allocated to the CPU at the moment, and thecomputational load waiting, for example, processes waiting in queue,with an additional priority rating in some cases (not shown). A record2201 t sums up the total of the parameter records of rows 2201 a-p forarray 101 a-p. Each processor in array 101 a-p may actually be a chipcontaining multiple CPUs or multiple cores of its own, so, in the caseof array 2101 a-p, the actual number of processors involved may be, forexample, 256, instead of 16, if each chip were to contain 16 cores.

FIG. 12 shows an exemplary process 2300 of the management softwareexecuted in any one of the processors of array 2101 a-p or in adedicated processor (not shown), according to one embodiment of thepresent disclosure. In step 2301 the system starts, and in step 2302 itstarts a count of the number of process repetitions in one session. Instep 2303 the system checks to see whether the count exceeds a pre-setmaximum, which in this example is P, the number of units in array 2101a-p that must be addressed. It is clear that because P represents anumber, there is no practical limitation to the numeric value of P. Ifthe count does not exceed the set maximum (NO), in step 2304 the systemreceives current readings from unit N, which in this example is chip2101 n. Each chip, as noted previously, may contain multiple CPUs. Insome implementations, power need is assessed on a per-chip basis, whilein other implementations, power need is assessed for each separate CPUor core in a chip. In step 2305, the system obtains the desired powerusage, based on computational requirements and priority between therequirements, from each software instance. In step 2306 the systemcalculates the power allocation and returns it to the process. In step2307 data about the exchanges in steps 2304-2306 is written to and/orread from table 2200. In step 2308, N is incremented and the processloops back to step 2303 until all cores in the array have beenaddressed, in sequence. If, in step 2303, the full sequence of units hasbeen addressed and N becomes greater than P (YES), the process moves tostep 2309, where the system calculates the power used, the desiredpower, and the available power for all units that were addressed insteps 2304-2306. In step 2310 power is allocated, and in step 2311 thesystem negotiates with PSU 2102 about available power or availableadditional power, and then in step 2312 the system updates data in table2200. The process may end at step 2313, and then it may start againbased on some pre-set timer or on triggering by a change in powerrequirements or priorities. In other cases, the process may be set tocontinuously loop back to step 2302.

In the current disclosure as described in the discussions of FIGS.10-12, a system 2100 has a power allocation that it needs to manage.Each processor is allocated a certain base capacity and must requestmore capacity from a central resource manager. In addition, the centralresource manager can signal the processor that it requires it to releasecapacity (either urgently or more slowly). It is clearly possible forthe central resource manager to be duplicated for redundancy and for themanagers to remain synchronized. Note that because the power managercontrols the power state of the processor it can alter the actual loadthat is imposed, hence the available system capacity can be used toalter the power state of the processor. This feature is key to thisinvention, as the system can never over allocate capacity withoutrunning the risk of a “brown out.” In addition, the current inventionpermits consideration of a situation where an amount of capacity is onlyallocated for a fixed period of time and must be renewed periodically.

FIG. 13 shows a simplified overview of an exemplary larger powermanagement system 2400. In this example, multiple installations,typically printed circuit boards, of the type of system shown as system2100 are stacked vertically (although it is clear that such systemmultiples may be arranged vertically, horizontally, sequentially,networked, or in any other way). Each system 2100 a-n has CPUs 2101 a-pand PSU 2102, so that in system 2400 there are PSUs 2102 a-n. System2400 also contains air conditioning or cooling and heat sensors 2410 a-nand master PSUs 2402 a-n. In this example, the variable range a-n forPSU 2402 a-n simply indicates a variable, finite numeric quantity, andshould not be construed to be an exact number. Depending on the totalrequirements of PSUs 2102 a-n, a variable number of PSUs 2402 a-n may beturned on or turned off, thus keeping the system running optimally andreducing problems of overheating.

FIG. 14 shows an exemplary process 2500 of the system-level managementsoftware, according to one embodiment of the present invention. Inessence, process 2500 is similar to process 2300. Additionallyincorporated are controls of the air conditioning or cooling and heatsensors 2410 a-n. In step 2501 the system starts, and in step 2502, itcollects all data from PSU 2102 a-n. In step 2503 the system assessesoutside and inside temperatures of each PSU 2102 a-n and the currentheat loads, as well as available air conditioning or coolingperformance. In step 2504 additional main PSUs are accordingly added orremoved, and new power ceilings are distributed to CPUs 2101 a-n. Instep 2505 the process ends.

In some cases several of the nodes in a system may require greaterperformance (based on loading). The individual power managers requestcapacity and it is granted by the central resource manager (CRM) (forexample, 50 nodes request 5 units of extra capacity allowing fullexecution). If other nodes request the same capacity, the CRM cansimilarly grant the request (assuming that the peak loads do not align,or it may over allocate its capacity).

In the event of a power supply failure, the CRM detects such. The backupbattery, or any other suitable energy reserve, including but not limitedto mechanical storage (flywheel, pressure tanks etc.) or electronicstorage (all types of capacitors, inductors etc.), here all jointlyreferred to a “backup battery”, is capable of supplying power for 100 msat peak load, so the CRM has 100 ms to reduce the capacity to the newlimit of 450 units (actually it has double that this time if the batterycan be fully drained, because part of the load may be supplied by thesingle functioning power supply). The CRM signals each power controllerin each processor that it must reduce its usage quickly. This operationtakes a certain amount of time, as typically the scheduler needs toreact to the lower frequency of the system; however, it should beachievable within the 100 ms. After this point each processor is goingto be running at a lower capacity, which implies slower throughput ofthe system (each processor has 4.5 units of capacity, which is enoughfor minimum throughput).

Further adjustment of the system can be done by the CRM requestingcapacity more slowly from some processors (for example moving them topower down states) and using this spare capacity to increase performancein nodes that are suffering large backlogs. In addition, in anaggressive case, the backup battery can have some of its energyallocated for short periods to allow peak clipping (the processorrequests increase capacity and is granted it, but only for a fewseconds).

A similar mechanism can be used to allocate cooling capacity (althoughthe longer time constants make the mechanism easier).

A less aggressive system can allocate more total power and have morecapacity after failure; while more aggressive systems can allocate lesstotal power and not allow all processors to run at full power even inthe situation where redundancy is still active. More complex redundancyarrangements can be considered (e.g., N+1), etc. The key is thatcapacity is allocated to different processors from a central pool andthe individual processors must coordinate their use.

For a system where the individual processors are smaller and have betterlow power modes (i.e., bigger differences between high and low power)this approach is even more applicable. Communication to the CRM can bedone by any mechanism. The requirement is that it must be quick so thatthe failure case time constant can be met, at least for most of thenodes. It's likely that Ethernet packets or messages to boardcontrollers are sufficient.

Communications Features

A system and a method and architecture that allow many processors toshare limited communication resources with efficient power and speed, aswell as chip real estate and power consumption are provided. In generalterms, this goal is achieved by a variety of changes to typical systemarchitecture, signified by a typically chip internal (so calledon-board, but sometimes system internal) virtualized communicationfabric added between the multi-CPU cores (referred to as “the cores”)and the external communication ports for communicating with the outsideworld, both to external sources and to other multi-processor chips in alarge network. Typically, such networks are organized as trees, fattrees, meshes, hypercubes, or toroids, allowing each chip to communicatewith its neighbors.

FIG. 15 shows a midlevel architectural overview of a multiprocessor chip3400 according to one embodiment. The multiple processor cores 3415 a-nare, in this example, ARM Cortex A9, including the ARM NEON SIMDprocessor. Multiple communication ports 3407 connect to various devices,which are discussed in greater detail below. An auxiliary processor3445, such as a ARM Cortex M3, is used to power manage the processors3415 a-n and to wake them up, let them sleep, or put them to sleep asneeded, as well as to manage voltage/frequency scaling of the processorcores 3415 a-n for load-driven power management. An intelligentswitching fabric 3427 connects one or more peripheral elements 3417-3423on one side and the actual ports 3429, 3430 and 3452-3455 on the otherside. This switching fabric, which is discussed in greater detail below,allows various different elements to be used in different ways. Forexample, to reduce the number of ports connected, a communication mediaaccess control (MAC), such as MACs 3421 and 3422, actually is split inhalf. In another example of the function of the switching fabric,pending communication requests are managed by the auxiliary processor3445, which is intricately involved in managing the switching fabric.The switching fabric allows the processor(s) 3415 a-n to go into a sleepmode or to enter power down mode, while the auxiliary processor respondsto communication requests for those processors that are asleep or off,and keeps those requests hanging in the switching fabric until theprocessors are started again after which the auxiliary processor 3445then lets the processors 3415 a-n receive the data. Of particular useare the interfaces 3452-3455, which connect these chips to theneighboring chips. Elements 3424, 3425 and 3426 are extended beyondtheir respective standard functional parts as discussed throughout thisdocument, namely an ARM® generic interrupt controller GIC 3412, adebugging and testing unit Coresight Debug/JTAG section 3409, and anaccelerator coherence port (ACP) 3413 that all help maintain memory andI/O coherence, allowing the auxiliary processor core to interact“invisibly” with all kinds of aspects involved with both powermanagement and communication management to effect the use of the novelswitching fabric 1427.

FIG. 16 shows a slightly more detailed view of the switching fabric, asdoes FIG. 17. FIG. 15 in particular shows the different paths that canbe created within the switching fabric, as controlled by a set ofrouters 3504 and 3505, with one router for internal communications andthe other router for external communications, respectively, The routersthemselves are typical in such a system, for internal routing andexternal routing respectively. These routers are primarily responsiblefor arbitrating and managing the control signals of the various datapaths between the “processor side” 3501 of the MACs (or othercommunication units) and the external faced side of those communicationunits 3528-3555. Although distinct data paths are shown, not all pathsexist as physical connections. Rather, they can be made available aspart of the logical switching.

Reflection of Interrupts Between Application Processors and TheirAssociated Power Microcontrollers

In reference to FIG. 15, the SOC reflects interrupts between applicationprocessors and their associated power microcontrollers. The GIC reflectsthe processor 1415 a-n interrupt lines to the auxiliary processor toallow the auxiliary processor to wake the processor 1415 a-n cores whenan interrupt needs to be processed, as previously discussed, as well asin other locations herein.

Further, if an individual core is in dormant mode, then just sending theinterrupt to the core has little effect. Thus the system needs tomonitor the nIRQOUT and nFIQOUT signals so the interrupt goes to the GICand is then reflected out of those pins—this signals the PMU (aka theauxiliary processor) to wake up the core.

If the whole processor subsystem is powered down, the interrupts aresteered to the auxiliary processor where the event is seen. Most eventscause a wakeup of the subsystems, but the interrupt is not removed.Rather, it is retained and once a processor wakes up and is ready tostart, the interrupt is taken directly by the GIC. In some cases,interrupts are turned into level sensitive (or masking) to themicrocontroller so as not to bury the microcontroller in interrupts.

The auxiliary processor microcontroller 3445 enables visibility into theprocessor 3415 a-n application processor 3445 interrupts when theapplication processor goes into low power state, and then the auxiliaryprocessor knows to wake up the processor 3415 a-n application processor.In some cases, interrupts are turned into level sensitive interrupts (ormasked) to the microcontroller to not bury the microcontroller ininterrupts and overwhelm the system. In some other cases, themicrocontroller enables visibility into application processor interruptswhen application processors go into a low power state, thus themicrocontroller can know to wake up the application processor.

While the foregoing has been with reference to a particular embodimentof the invention, it will be appreciated by those skilled in the artthat changes in this embodiment may be made without departing from theprinciples and spirit of the disclosure, the scope of which is definedby the appended claims.

1. A system on a chip, comprising: one or more processing cores; one ormore management processors coupled to each one of the one or moreprocessing cores; one or more communication interfaces; and one or moreinterrupt controllers coupled between each one of the one or moreprocessing cores and the one or more management processors for enablingan interrupt transmitted for reception by a first one of the one or moreprocessing cores to be reflected to the one or more managementprocessors from the first one of the one or more processing cores whilethe first one of the one or more processing cores is in the inactivestate.
 2. The system on a chip of claim 1, further comprising: aswitching fabric coupled between the one or more processing cores, theone or more management processors and the one or more communicationinterfaces, wherein the one or more interrupt controllers coupled to theswitching fabric for enabling the interrupt transmitted for reception byat least one of the one or more processing cores to be reflected to theone or more management processors from the first one of the one or moreprocessing cores while the first one of the one or more processing coresis in the inactive state.
 3. The system on a chip of claim I wherein theone or more management processors cause the interrupt to be provided tothe first one of the one or more processing cores in response to thefirst one of the one or more processing cores being transitioned fromthe inactive state to an active state.
 4. The system on a chip of claim3 wherein: the interrupt is maintained by the one or more managementprocessors until the first one of the one or more processing cores beingtransitioned from the inactive state to the active state; and theinterrupt is handled directly by the one or more interrupt controllersin response to the first one of the one or more processing cores beingtransitioned from the inactive state to the active state.
 5. The systemon a chip of claim 1 wherein: the one or more management processorscause the interrupt directed to the first one of the one or moreprocessing cores to be held in the switching fabric while the first oneof the one or more processing cores is in the inactive state; the one ormore management processors assess the one or more processing cores todetermine a second one of the one or more processing cores that iscurrently in an active state; and the one or more management processorscause the communication request to be delivered to the second one of theone or more processing cores for allowing the second one of the one ormore processing cores to perform the task initiated by the communicationrequest after determining that the second one of the one or moreprocessing cores is currently in the active state.
 6. The system on achip of claim 5 wherein: the one or more management processors assessthe second one of the one or more processing cores to determine anavailable processing power capacity prior to causes the communicationrequest to be delivered to the second one of the one or more processingcores; and the one or more management processors cause the communicationrequest to be delivered to the second one of the one or more processingcores in response to determining that the second one of the one or moreprocessing cores has sufficient processing power available forperforming the task to be initiated by the communication request.
 7. Acomputing system, comprising: one or more server on a chip units eachhaving one or more processing cores and one or more power managementportions coupled between each one of the one or more processing coresone or more processing cores; one or more interconnect portions coupleto each one of the one or more server on a chip units for enabling thecomputing system to be communicatively connected to one or more othercomputing systems; and one or more interrupt controllers coupled betweeneach one of the one or more processing cores and the one or more powermanagement portions for enabling an interrupt transmitted for receptionby a first one of the one or more processing cores to be reflected tothe one or more management processors from the first one of the one ormore processing cores while the first one of the one or more processingcores is in the inactive state,
 8. The computing system of claim 7wherein: the one or more server on a chip units each include a switchingfabric coupled between the one or more processing cores, the powermanagement portions and the one or more communication interfacesthereof, and the one or more interrupt controllers are coupled to theswitching fabric for enabling the interrupt transmitted for reception byat least one of the one or more processing cores to be reflected to theone or more management processors from the first one of the one or moreprocessing cores while the first one of the one or more processing coresis in the inactive state.
 9. The computing system of claim 7 wherein theone or more power management portions cause the interrupt to be providedto the first one of the one or more processing cores in response to thefirst one of the one or more processing cores being transitioned fromthe inactive state to an active state.
 10. The computing system of claim9 wherein: the interrupt is maintained by the one or more powermanagement portions until the first one of the one or more processingcores being transitioned from the inactive state to the active state;and the interrupt is handled directly by the one or more interruptcontrollers in response to the first one of the one or more processingcores being transitioned from the inactive state to the active state.11. The computing system of claim 7 wherein: the one or more powermanagement portion cause the interrupt directed to the first one of theone or more processing cores to be held in the switching fabric whilethe first one of the one or more processing cores is in the inactivestate; the one or more power management portion assess the one or moreprocessing cores to determine a second one of the one or more processingcores that is currently in an active state; and the one or more powermanagement portion cause the communication request to be delivered tothe second one of the one or more processing cores for allowing thesecond one of the one or more processing cores to perform the taskinitiated by the communication request after determining that the secondone of the one or more processing cores is currently in the activestate.
 12. The computing system of claim 11 wherein: the one or moremanagement processors assess the second one of the one or moreprocessing cores to determine an available processing power capacityprior to causes the communication request to be delivered to the secondone of the one or more processing cores; and the one or more managementprocessors cause the communication request to be delivered to the secondone of the one or more processing cores in response to determining thatthe second one of the one or more processing cores has sufficientprocessing power available for performing the task to be initiated bythe communication request.
 13. A computing system, comprising: one ormore server on a chip units each having one or more processing cores andone or more power management portions coupled between each one of theone or more processing cores one or more processing cores; one or moreinterconnect portions couple to each one of the one or more server on achip units for enabling the computing system to be communicativelyconnected to one or more other computing systems; one or more interruptcontrollers coupled between each one of the one or more processing coresand the one or more power management portions for enabling an interrupttransmitted for reception by a first one of the one or more processingcores to be reflected to the one or more management processors from thefirst one of the one or more processing cores while the first one of theone or more processing cores is in the inactive state operating systemsoftware accessible by each one of the one or more processing cores ofthe one or more server on a chip units; and a first memory structurecoupled to one or more direct memory access portions of each one of theone or more server on a chip units for providing direct access memoryfunctionality within the computing system.
 14. The computing system ofclaim 13 wherein: the one or more server on a chip units each include aswitching fabric coupled between the one or more processing cores, thepower management portions and the one or more communication interfacesthereof; and the one or more interrupt controllers are coupled to theswitching fabric for enabling the interrupt transmitted for reception byat least one of the one or more processing cores to be reflected to theone or more management processors from the first one of the one or moreprocessing cores while the first one of the one or more processing coresis in the inactive state.
 15. The computing system of claim 13 whereinthe one or more power management portions cause the interrupt to beprovided to the first one of the one or more processing cores inresponse to the first one of the one or more processing cores beingtransitioned from the inactive state to an active state.
 16. Thecomputing system of claim 15 wherein: the interrupt is maintained by theone or more power management portions until the first one of the one ormore processing cores being transitioned from the inactive state to theactive state; and the interrupt is handled directly by the one or moreinterrupt controllers in response to the first one of the one or moreprocessing cores being transitioned from the inactive state to theactive state,
 17. The computing system of claim 13 wherein: the one ormore power management portion cause the interrupt directed to the firstone of the one or more processing cores to be held in the switchingfabric while the first one of the one or more processing cores is in theinactive state; the one or more power management portion assess the oneor more processing cores to determine a second one of the one or moreprocessing cores that is currently in an active state; and the one ormore power management portion cause the communication request to bedelivered to the second one of the one or more processing cores forallowing the second one of the one or more processing cores to performthe task initiated by the communication request after determining thatthe second one of the one or more processing cores is currently in theactive state.
 18. The computing system of claim 17 wherein: the one ormore management processors assess the second one of the one or moreprocessing cores to determine an available processing power capacityprior to causes the communication request to be delivered to the secondone of the one or more processing cores; and the one or more managementprocessors cause the communication request to be delivered to the secondone of the one or more processing cores in response to determining thatthe second one of the one or more processing cores has sufficientprocessing power available for performing the task to be initiated bythe communication request.
 19. The computing system of claim 13, furthercomprising: a second memory structure coupled to one or more memoryinterfaces of each one of the one or more server on a chip units forproviding persistent storage functionality within the computing system.20. The computing system of claim 19 wherein the one or more memoryinterfaces of the one or more server on a chip units includes at leastone of: a NAND flash interface; a eMMC interface; a PCIe interface; aSATA interface; a SD interface; and a SAS interface.
 21. The computingsystem of claim 19 wherein the one or more memory interfaces of the oneor more server on a chip units includes: a eMMC interface; a PCIeinterface; a SATA interface; a SD interface; and a SAS interface.